Qualcomm's HBC is now working silicon: stacked LPDDR on a compute die, aimed at the cost of moving data

Qualcomm says the first generation of High Bandwidth Compute (HBC), the memory architecture it unveiled at its June investor day, has passed silicon validation in its San Diego lab. The validated part does full reads and writes and runs near-memory computation, so both halves of the design work in silicon.

What HBC is

HBC stacks several layers of LPDDR, the low-power DRAM used in phones and in Qualcomm's current AI200 card, and connects the layers vertically with through-silicon vias (TSVs). The dies are joined by wafer-to-wafer bonding. Under the stack sits a base die that acts as a compute engine for AI inference, and work can be offloaded to it so it runs next to the data instead of on a distant accelerator.

The shape is familiar from HBM, which also stacks DRAM dies on TSVs. HBM4 goes further than earlier generations by making its base die a logic die, which pulls more control and I/O-preparation work into the stack. HBC differs in two ways. It uses LPDDR instead of HBM's DRAM dies, trading some peak speed per pin for lower energy per bit. And it puts real inference compute in the base die, not only interface logic. The aim is to shrink the distance data travels from centimetres, across a package to a separate compute die, to micrometres, straight down through the stack.

The numbers, and what they measure

• 133 TB/s is the total memory bandwidth of an AI250 accelerator card, not the bandwidth of one HBC stack. Qualcomm puts it at 18x the LPDDR5X on the AI200 card.
• Bandwidth per watt is the headline claim. In June Qualcomm cited roughly 6x HBM. With the validation news it says more than 5x projected HBM4 specifications. That compares Qualcomm's measured silicon with someone else's spec sheet, and it has not been independently tested.
• Timing: HBC Gen 1 arrives with the Dragonfly AI250, which is due to sample in the first half of 2027. Volume shipments will come later. Qualcomm has said HBC Gen 2 will go into the AI300, and that it has a roadmap to use HBC across its accelerator line.

Why it matters

In AI inference, the bottleneck is usually getting weights and the KV cache to the compute units, not the arithmetic itself, and moving those bytes costs much of the energy. HBM answers with raw bandwidth, but it is expensive, made by only three suppliers, and sold out into 2027. HBC is a bet that an inference accelerator can avoid HBM supply and cost altogether by building around commodity low-power DRAM and moving the compute to the memory. It also helps explain why Qualcomm could win a multi-generational AWS design deal as a newcomer to data-centre silicon.

What to watch

Whether AI250 samples ship in the first half of 2027 and hit 133 TB/s on customers' benches, independent bandwidth-per-watt figures against shipping HBM4 rather than projections, yield and thermals on a logic die buried under a DRAM stack, and which memory makers build the LPDDR stacks.