Leading-Edge Chips

TSMC's 7nm+ became the first high-volume node using ASML's extreme-ultraviolet machines — the tool that unlocked everything below 7nm.

Samsung's 3nm was the first to ship GAA transistors, the architecture now succeeding FinFET at the frontier.

High-bandwidth memory became the other scarce frontier part, with SK hynix leading supply for AI GPUs.

All three leaders entered 2nm-class volume in 2025 (TSMC N2 in Q4); demand outstrips supply, with long foundry waitlists.

IBM demonstrated the world's first sub-1nm (0.7nm / 7Å "nanostack") logic transistor architecture, experimentally validated at the 2026 VLSI Symposium with functional CMOS inverters and ~100B transistors on a fingernail-sized die. A research milestone — not a product: IBM is still scaling 2nm and sees production as early as ~5 years out. (Aggregator coverage conflated this with the separate 'Anderon' quantum-chip foundry plan.)

Intel's 18A brought PowerVia backside power to a volume node — a structural change rivals are still adopting.

President Trump said (on Truth Social, 18 Jun 2026) that Apple has agreed to work with Intel on US chip design and manufacturing — sending Intel up ~9%. It follows a WSJ report of a preliminary deal after a year of talks, with Intel likely starting on simpler M-series parts before iPhone silicon, helping Apple diversify from TSMC. Neither company has confirmed scope, timing or structure — so this remains unconfirmed.

TSMC and Samsung committed to using ASML's High-NA EUV scanners — Samsung by 2028, TSMC by 2030 — ending the question of whether the leading foundries would adopt the tool or route around it with multipatterning. Intel got there first and is already running High-NA. The same week the three joined an ASML initiative to move photomasks from today's 6-inch format to 12-inch, targeting a pilot line in 2031 and advanced-node production in 2033. The mask size is the real constraint: Intel's SPIE data shows that stitching two exposures, which today's masks force at High-NA field sizes, cuts scanner output from about 175 wafers per hour to about 125 — a ~30% productivity loss.

The next frontier (TSMC A14, Intel 14A, Samsung SF1.4), with High-NA EUV — targeted around 2028, not yet here.